The fetch-decode-execute loop only works if the chip and the program agree on what the bytes mean. That agreement is the Instruction Set Architecture, or ISA — the most consequential interface in computing, and the longest-lived. The ISA is why your Linux laptop can run a binary compiled in 1995, why an iPhone game runs on devices built years apart, and why Apple's switch to its own silicon was a multi-year migration of an entire software ecosystem.
The contract
An ISA specifies, in unambiguous language, what bytes a CPU will accept and what they mean. It defines:
- The encoding of instructions — exactly which bits represent ADD, which represent LOAD, which represent BRANCH-IF-EQUAL.
- The set of architectural registers — how many, how wide, what they are named, and which ones have special behaviour (the program counter, the stack pointer).
- The memory model — how loads and stores interact, what guarantees the chip provides about the order of memory operations across cores.
- The exception model — what happens when the CPU divides by zero, or hits an unmapped page, or receives an interrupt.
- System-level state — privileged registers, page-table format, virtual-memory rules, security boundaries.
An ISA is a specification document: hundreds or thousands of pages, written in pedantic English with formal pseudo-code. The Intel x86-64 manual runs to roughly 5,000 pages. The Arm ARMv9 reference is similar. Every implementation — Intel chips, AMD chips, the dozens of ARM licensees — must obey the manual.
Two tribes — CISC and RISC
Through the 1980s, two design philosophies emerged.
CISC (complex instruction set computer): rich, expressive instructions. A single x86 instruction can read two memory locations, multiply their contents, and write the result back to a third. Variable-length encoding (1–15 bytes). Hundreds of instructions, many baroque. The argument: instructions are scarce, memory is precious, packing more semantics into each instruction reduces program size and reduces the number of fetches.
RISC (reduced instruction set computer): austere, regular instructions. Each instruction does one thing — load, store, register-to-register arithmetic — in a fixed-length encoding (4 bytes), with a small instruction count (~50 in baseline RISC-V). The argument: simple instructions can be pipelined and clocked faster; let the compiler do the work of composing complex behaviour from simple parts.
RISC won the technical argument decisively in the 1990s. ARM, MIPS, PowerPC, SPARC — all RISC, all faster per gate than the CISC architectures of the same era. Hennessy and Patterson's Computer Architecture textbook is, structurally, a treatise on the victory of RISC.
And yet — Intel x86, the most commercially successful CISC architecture, never died. It survived because of microarchitectural cleverness: modern x86 chips internally translate CISC instructions into a stream of RISC-like µops as part of decoding, then execute those µops in a deeply pipelined, out-of-order RISC core. The ISA stayed CISC; the implementation became RISC. The contract was preserved; the engine underneath was replaced.
ISA vs microarchitecture
This brings us to one of the most useful distinctions in computer architecture: ISA versus microarchitecture. The ISA is the visible contract — the bytes the CPU will accept and the abstract behaviour it promises. The microarchitecture is the actual circuitry inside the chip — the pipeline depth, the cache sizes, the branch predictor, the number of execution ports, the schedulers, the renamers. Microarchitecture is invisible to programs; it can be redesigned every generation. ISA is visible; it cannot.
An Intel Pentium from 1993 and a Core i9 from 2024 implement nearly the same ISA. The Core i9 is roughly 100,000× faster, in some workloads. Almost none of that speedup came from the ISA. It came from microarchitectural inventions — better caches, deeper pipelines, branch prediction, out-of-order execution, simultaneous multithreading, vector units, prefetchers, speculation. The ISA was a stable promise; the chip beneath it was rebuilt every few years.
The ISA is the most stable thing in the computing stack. The transistors below it change every two years. The software above it changes every week. The ISA, once defined, lives for decades.
Forty years of x86
Consider x86. Defined in 1978 with the Intel 8086. Extended to 32 bits in 1985 with the 80386. Extended to 64 bits in 2003 with AMD's Opteron. SIMD instructions added through the 1990s and 2000s (MMX, SSE, AVX, AVX-512). Vector and matrix instructions added in the 2020s (AMX). Almost every x86 binary compiled in the last forty years still runs on a modern x86-64 machine. The same bytes still mean the same thing.
This stability is not aesthetic; it's economic. An ISA migration is a multi-year, multi-billion-dollar undertaking. Apple managed it twice (PowerPC → x86 in 2006, x86 → ARM in 2020), each time only by means of a binary translator (Rosetta) that pretended the old ISA still worked while the ecosystem caught up. ARM is succeeding in displacing x86 in laptops and servers in the 2020s — and even so, the displacement is taking a decade.
The GPU's parallel ISA
A GPU has an ISA too, though it is shaped very differently. NVIDIA's GPUs implement PTX (Parallel Thread Execution) as a virtual ISA, which is then JIT-compiled to a hardware-specific real ISA called SASS at run time. PTX has SIMD-style instructions: a single instruction operates on 32 lanes simultaneously (a "warp"), each lane working on different data. There are tensor instructions that do entire 16×16 matrix multiplies in a single op. The contract is fundamentally different from a CPU's, because the workload is fundamentally different — every modern AI workload is, deep down, billions of identical operations on different data.
We will spend a whole chapter on what that means architecturally — Chapter 28, "The GPU's Different Mind." For now, the lesson is just that the ISA, whatever shape it takes, is the place where the software stops talking about transistors and the hardware stops talking about programs. Above the ISA: code. Below it: circuits. The interface is the most carefully engineered seam in the digital world.
Through the 2010s, an open-source ISA called RISC-V emerged from UC Berkeley. Anyone can implement it without paying licensing fees. It is small, modern, modular. Most major hyperscalers and AI startups have RISC-V projects underway, sometimes for the main CPU, often for in-chip controllers and accelerators. Whether RISC-V displaces ARM in mass-market silicon is one of the open questions of the next decade. As of 2026, it is winning quietly, in a thousand corners of every chip.
We have, by now, climbed from electrons to instructions. We have a chip that runs programs. The remaining mystery is where the program lives, how it gets to the chip, and how the chip survives the fact that the memory it reads from is, in the most literal sense, much, much slower than itself.