What does CoWoS stand for?	Chip-on-Wafer-on-Substrate — describing the two-step assembly order: GPU and HBM bond to an interposer wafer, then the interposer wafer bonds to an organic substrate.
How many DRAM dies are in a single HBM4 stack?	12 to 16 dies, stacked on a base logic die.
What is the HBM4 interface width?	2,048 bits — double the 1,024-bit width of the original HBM generation.
How much memory and bandwidth does Rubin’s HBM4 deliver per GPU?	288 GB at 22.2 TB/s.
What connects each DRAM die to the one below it in an HBM stack?	Through-silicon vias (TSVs) — tens of thousands of vertical conductors piercing each die from top to bottom.
What is the approximate interposer area for the H100-generation CoWoS-S versus Rubin’s CoWoS-L?	~2,500 mm² for CoWoS-S; ~4,700 mm² for the CoWoS-L variant used with Rubin.
What are micro-bumps?	Tiny copper-tin pillars that solder die to interposer at extraordinarily fine pitch, providing the high-density electrical connections between GPU, HBM, and interposer.
Why is CoWoS called a 2.5D architecture?	It is not fully stacked (3D) nor fully flat (2D) — dies sit side-by-side on an interposer rather than directly atop one another, capturing most vertical-integration bandwidth gains without the thermal problems of stacking compute on compute.
Since when has CoWoS capacity been a binding constraint on AI hardware shipments?	Since 2023 — NVIDIA’s CoWoS allocation is one of the most carefully negotiated quantities in the industry.